Current Issue : July - September Volume : 2015 Issue Number : 3 Articles : 4 Articles
In the last few years speed of processor is increase every six month to one year. We have requirement of parallel processing for some scientific research work such as bio-medical research, earthquake analysis and for high definition video. For parallel processing we have to require multi-core architecture. With Multi-core architecture we can improve system performance up to some limitation because we can’t reduce transistor size. Multi-core means more than one similar type of core always in even number is integrated on single chip with given area. If we reduce transistor size then density of transistor on chip is increase but heating effect increase it affects working of processor and some time processor chip become useless.In heterogeneous architecture all core are different in size, frequency and functionality also different instruction set is used for programming. With help of Reconfigurable heterogeneous architecture we can improve the performance of the system. Heterogeneous architecture means combination of CPU, GPU, DSP and FPGA processor integrate on single chip. In Today’s PC and Laptop there are CPU and GPU both are integrate on single chip, with this combination we can achieve high speed. In future Different combination like CPU with DSP, CPU with FPGA and all are integrate on single chip for improvement of speed and performance of system with limited area and given power budget. Reconfigurable Architecture means we implement our hardware and software both on FPGA chip, We can easily expand our system with help of reconfigurable architecture that support future application with just change in architecture and software without change whole system. So we can reduce cost of electronic gadgets with help of reconfigurable heterogeneous architecture....
The goal of this paper is to describe an active decentralized fault-tolerant control (ADFTC) strategy based on dynamic output\nfeedback for reconfigurable manipulators with concurrent actuator and sensor failures. Consider each joint module of the\nreconfigurable manipulator as a subsystem, and treat the fault as the unknown input of the subsystem. Firstly, by virtue of\nlinear matrix inequality (LMI) technique, the decentralized proportional-integral observer (DPIO) is designed to estimate and\ncompensate the sensor fault online; hereafter, the compensated system model could be derived. Then, the actuator fault is estimated\nsimilarly by another DPIO using LMI as well, and the sufficient condition of the existence of H? fault-tolerant controller in the\ndynamic output feedback is presented for the compensated system model. Furthermore, the dynamic output feedback controller\nis presented based on the estimation of actuator fault to realize active fault-tolerant control. Finally, two 3-DOF reconfigurable\nmanipulators with different configurations are employed to verify the effectiveness of the proposed scheme in simulation.The main\nadvantages of the proposed scheme lie in that it can handle the concurrent faults act on the actuator and sensor on the same joint\nmodule, as well as there is no requirement of fault detection and isolation process; moreover, it is more feasible to the modularity\nof the reconfigurable manipulator....
Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs).\nHowever, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we\npresent a two-clock-cycle latency NoC micro architecture. An efficient request masking technique is proposed to combine virtual\nchannel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area\noverhead, operating frequency, and quality-of-service (QoS).We evaluate our NoC against CONNECT, an open source low latency\nNoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our\nNoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%?20%\nhigher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover,\nthe proposed NoC router achieves 2.3 times better performance compared to CONNECT....
Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity\nincreases and new services are deployed, both high throughput and reconfigurability are required for packet classification\narchitectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly\ndeveloped as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In\nthis context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables\ncomparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of\nlookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for\nfuture networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation\nresults for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases,\ndemonstrating the benefits of our proposed optimization....
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